In modern computer systems, the need to perform data storage and retrieval operations at high speeds is often critical. Unfortunately, however, these rates can often be limited by, for example, the limited speeds at which at least some conventional memory control systems operate during the performance of such data storage and retrieval operations.
Various factors can limit the speeds at which memory control systems operate. By example, in at least some conventional memory control systems, wherein data is transferred between memory controller and memory device components during `read` and `write` operations, there may be differences between the times at which portions of the data arrive at the individual components. These differences may result from, for example, the use of interface buses having different lengths for coupling the memory controller to the memory device components, and/or the presence of variations in the amount of data loading on the buses. Such differences can cause errors to occur during the `read` and/or `write` operations, and can limit the operating speed of the memory control system since, for example, a microprocessor of the computer system may need to delay performing an operation until all of the data portions are successfully `written` to and/or `read` from the memory.
Reference is now made to FIG. 8, which shows various components of a memory control system (hereinafter referred to as a "memory subsystem") of a conventional computer system. In particular, FIG. 8 shows a memory controller 70 that is coupled to memory devices 55a-55d through buses 54a-54d, respectively. Memory controller 70 is employed for `writing` data to, and for `reading` data from, the memory devices 55a-55d through the buses 54a-54d. The memory controller 70 includes 4-bit registers 70a-70d, which are assumed to have a capability for being enabled for a predetermined time period (also referred to as an "enablement period"), in response to receiving individual positive edges 71 of a pulsed clock signal through input CP1. Data that is received by the registers 70a-70d during the enablement period is accepted (i.e., loaded) by these devices 70a-70d, for subsequent transfer to, for example, a microprocessor (not shown).
Memory devices 55a-55d are assumed to be memory chips, such as, for example, Dynamic Random Access Memory (DRAM) chips, and are each assumed to have a capability for being enabled for a predetermined time period, for accepting (i.e., loading) data received over buses 54a-54d, in response to receiving individual positive edges 59 of a pulsed clock
As was previously described, in at least some conventional memory subsystems, such as the one represented in FIG. 8, there may be variations in the lengths of the buses 54a-54d coupling the devices 70 and 55a-55d. These variations may be a result of, for example, the use of memory devices 55a-55d and associated buses 54a-54d manufactured in accordance with different manufacturing tolerances/specifications. The variations in the lengths of the buses 54a-54d can cause data 53a-53d that is simultaneously transmitted from the registers 70a-70d of memory controller 70 during a write operation, to eventually arrive at the respective memory devices 55a-55d at different times, and at times that are not within a duration of a same enablement period of the respective memory devices 55a-55d. This can result in `write` errors. A similar problem can also arise during `read` operations where data is provided from the memory devices 55a-55d to the memory controller 70, resulting in `read` errors.
For memory subsystems that include multiple memory modules (e.g., dual in-mode memory modules), wherein one or more memory devices 54a-55d are arranged on the memory modules, different ones of the memory modules may be manufactured in accordance with different manufacturing tolerances/criteria. As a consequence, there may be a great number of variations between the lengths of buses employed for coupling a memory controller to the different memory modules. As such, in these types of memory subsystems the above-described problems can be even more severe.
It is known to increase the speeds at which memory subsystems operate by employing techniques for reducing the overall amount of time required to successfully read and write data to individual memory chips, and by employing parallel memory chips. Extended-Data-Out (EDO) mode memory devices, Synchronous Dynamic Random Access Memory (SDRAM) devices, and Synchronous Dynamic Random Access Memory Double Data Rate (SDRAM-DDR) devices are examples of recent developments for increasing memory subsystem operating speeds. Memory subsystems that employ SDRAMs are synchronous (i.e., data is sent upon an occurrence of a positive edge of a clock signal pulse, and data is received upon an occurrence of a positive edge of a different clock signal pulse). In memory subsystems employing SDRAM-DDR devices, data can be sent upon an occurrence of a positive edge of a clock signal pulse, and received upon a negative edge of the same clock signal pulse. This capability allegedly reduces subsystem latency in half relative to the latency of subsystems that do not employ SDRAM-DDR devices. Memory subsystems that include SDRAM-DDR devices typically employ so called data strobes, which are sent along with data being transferred. Unfortunately, such data strobes require the use of extra pins and wiring, can increase system latency, and can cause an increase in the amount of time required for the memory subsystem to transition between `read` and `write` operations. In view of the foregoing considerations, it can be appreciated that it would be desirable to provide a technique which optimizes the performance of a memory subsystem by overcoming the above-described problems. It would also be desirable that the technique not require the use of extra signals or additional memory device circuitry, or require an increase in system latency, or an increase in the length of time needed to transition between `read` and `write` operations.